According to the examination by the inventors of the present invention, the following micro-fabrication technology for DRAM is known.
In order to microfabricate and highly integrate the memory cells of DRAM, capacitors that realize a large capacity in a limited base area of the memory cells and miniaturized transistors are required. A serious problem at the time of microfabricating memory cell transistors is the thickness reduction of gate oxide. When a gate length of MOS transistors is shortened, it is necessary to reduce the thickness of the gate oxide in order to suppress a short channel effect.
In DRAM, however, since an N channel MOS transistor is used for a memory cell, a maximum writing voltage for an “H” side of a storage node is VPP−VT which is obtained when the voltage VPP on an “H” side of a word line to be applied to a gate of the memory cell transistor reduces by a threshold voltage VT, and the threshold voltage VT is not allowed to be reduced in order to maintain data retention characteristics. For this reason, the voltage of the word line cannot be readily reduced. Therefore, in comparison with the MOS transistors to be used for logic products, the thickness of the gate oxide of memory cell transistors is large, and thus the micro-fabrication thereof is difficult.
In order to solve such a problem, for example, Japanese Patent Application Laid-Open Publication No. 11-260054 (Patent Document 1) discloses DRAM in which a plate electrode of a memory cell is driven to increase the writing voltage to the memory cell. In this method, the voltage on the “H” side of a word line is reduced. By doing so, the problem that the writing of the “H” side data becomes insufficient is compensated by driving a plate electrode. As a result, since the thickness of a gate oxide of a memory cell transistor can be reduced, the memory cell can be microfabricated.